The present invention relates to a phase-locked loop circuit, and a recording/reproducing apparatus including the phase-locked loop circuit.
Recording/reproducing apparatuses such as a magnetic recording apparatus, an optical disk apparatus, and a digital audio tape recorder (DAT) use a phase-locked loop circuit (to be referred to as a PLL hereinafter) because a clock phase-locked with reproduction data by using the reproduction data is required in reproduction. The PLL locks the phase of a clock generated upon reception of reproduction data.
In recording data on a recording medium such as a disk or a tape, data is temporarily digitally modulated and then recorded. In this modulation, a data string of m (m is an integer equal to or larger than 1) bits is generally converted into a code string of n (n is an integer larger than m) bits. Since conversion is performed with n&gt;m, the number of types of code strings is larger than that of data strings. In this way, the number of successive "0"s is limited small in the code string. As a result, "0"s do not successively appear for a long time to allow to extract a reproduction clock from reproduction data using the PLL.
FIG. 20 shows a code string (a), a clock (f), and a recording signal (p). This code string (a) is a code string upon modulation, and is generated in synchronism with the clock (f) having a period T. The recording signal (p) is a pulse signal corresponding to the code string (a), and the pulse interval is an integer multiple of the period T. By limiting the maximum value of the pulse interval between pulse signals corresponding to many types of code strings (a) converted with n&gt;m, pulse signals can be recorded on the recording medium at a desired pulse interval.
On the other hand, in reproducing data recorded on the recording medium, a reproduction clock equivalent to the clock (f) is required. The reproduction clock must have the same frequency and phase as those of the recording signal (p), and is generated using the PLL. However, reproduction data input to the PLL has an irregular pulse interval, as represented by the recording signal (p). To generate the reproduction clock using this pulse, an apparatus associated with the present invention comprises a PLL having two loops like the one shown in FIG. 21.
The first loop comprises an input terminal 173 for receiving reproduction data, a phase comparator 176 for comparing the phase of the reproduction data with that of a reproduction clock output from a voltage-controlled oscillator (to be referred to as a VCO hereinafter) 180, a selector 177 for selecting and outputting one of outputs from the phase comparator 176 and a frequency comparator 175, a charge pump 178 for converting the input phase comparison signal or frequency comparison signal into a corresponding current signal, a loop filter 179 operating as a low-pass filter for receiving the current signal and converting it into a low-frequency voltage signal, and the VCO 180 for outputting a signal having a frequency corresponding to the output voltage of the loop filter 179. The first loop performs feedback control so as to make the phase of the reproduction clock output from the VCO 180 phase-lock with that of the reproduction data.
The second loop comprises an input terminal 171 for receiving a reference clock, the frequency comparator 175 for comparing the frequency of the reference clock with that of the reproduction clock, the selector 177, the charge pump 178, the loop filter 179, and the VCO 180. The second loop performs feedback control so as to make the frequency of the reproduction clock output from the VCO 180 coincide with that of the reference clock.
The two loops are selected when a switching control signal is input to an input terminal 172 to switch the output of the selector 177. If both the data recording and reproducing periods exist, no reproduction data is input from the input terminal 172 during the recording period. During this period, the second loop is selected to control the output frequency of the VCO 180 so as to coincide with the frequency of the reference clock. Accordingly, even while no reproduction data is input, the reproduction clock output from the VCO 180 can be brought close to a desired frequency. When the recording period shifts to the reproducing period, and reproduction data is input, the first loop is selected, and the reproduction clock is so controlled as to phase-lock with the reproduction data.
Control using only the first loop cannot make the output from the VCO 180 phase-lock with that of the reproduction data while no reproduction data exists. In this state, even if the period shifts to the reproduction period, reproduction data is input, and phase comparison control is performed, the frequency of the output from the VCO 180 cannot be made to coincide with a single frequency of the reproduction data. At many frequencies different from the frequency of the reproduction data, the charge and discharge amounts of the capacitance in the loop filter 179 undesirably coincide with each other to falsely lock the output from the VCO 180. To avoid this phenomenon, the second loop is used during the recording period.
As shown in FIG. 22, the phase comparator 176 comprises an input terminal 191 for receiving reproduction data, an input terminal 192 for receiving the reproduction clock from the VCO 180, D flip-flops 195 to 197, an invertor 200, AND circuits 198 and 199, an output terminal 193 for outputting the phase lag amount, and an output terminal 194 for outputting the reference amount. The phase lag amount corresponds to the phase lead amount of the reproduction clock with respect to the reproduction data. When the phase of the reproduction clock is lagged from that of the reproduction data, the pulse width of the phase lag amount becomes larger than that of the reference amount; when the phase of the reproduction clock is led from that of the reproduction data, the pulse width of the phase lag amount becomes smaller than that of the reference amount; and when the two phases lock with each other, the pulse widths become equal to each other.
FIG. 23 is a timing chart showing reproduction data (b) in this case, a code string (a) corresponding to the reproduction data (b), a reproduction clock (f), outputs (q), (r), and (s) from the flip-flops 195, 196, and 197, a phase lag amount (t), and a reference amount (u). For one period T of the code string, the period of the reproduction data (b) is 1/2.multidot.T. The pulse widths of the phase lag amount (t) and the reference amount (u) are equal to the pulse width (1/4.multidot.T) of the reproduction clock (f).
The reproduction data (f) naturally fluctuates in the time axis direction due to noise. In FIG. 23, if the reproduction data (b) fluctuates greatly over a range TV having a size of 1/2.multidot.T, the output phase lag amount (t) represents erroneous phase comparison information. In recent years, the quality of a reproduction data signal is easily degraded by a decrease in signal-to-noise ratio (to be referred to as an S/N ratio hereinafter) of a reproduction signal because the reproduction signal becomes smaller along with an increase in recording density, or by an increase in defects of a recording medium. Particularly in the DAT, a signal may be omitted owing to high-speed search, which disadvantageously varies the phase and frequency of a clock. This disadvantage fluctuates the reproduction data over the range TV to output erroneous phase comparison information. In reproducing data, the phase locking of the PLL is stepped out to continuously generate errors. The reliability of the recording/reproducing apparatus greatly decreases.
FIGS. 24A and 24B show the output voltage of the charge pump 178 when the frequency of the reproduction data falls outside the lockable pull-in range of the PLL. FIG. 24A shows the case wherein the reference clock frequency is 10 MHz, and the reproduction data frequency is 8 MHz. In many cases, the frequencies of the reference clock and the reproduction data do not coincide with each other. Before reproduction data is input, the second loop is selected to make the periods of the reference and reproduction clocks coincide with each other. When the second loop is switched to the first loop, and reproduction data is input, the reproduction data should be ideally locked at 8 MHz as represented by the dotted line, but only repeatedly changes in voltage at a predetermined period and cannot be locked as represented by the solid line.
FIG. 24B shows the case wherein the reference clock frequency is 10 MHz, and the reproduction data frequency is 12 MHz. While the second loop is selected, the PLL is synchronized with the reference clock. When the second loop is switched to the first loop, and reproduction data is input, the reproduction data should be ideally locked at 12 MHz as represented by the dotted line, but the reproduction data only repeatedly changes in voltage at a predetermined period and cannot be locked as represented by the solid line.
In this manner, when the frequencies of the reference clock and the reproduction data exceed a predetermined ranges, the reproduction clock may not converge at the frequency of the reproduction data, and cannot be phase-locked with the reproduction data.
As described above, the phase comparator shown in FIG. 21 is poor in noise resistance. If the frequencies of the reference clock and the reproduction data do not substantially coincide with each other, the frequency of the reproduction clock cannot follow that of the reproduction data.